Digital processing systems often employ a cache memory to overcome the data transfer delay associated with communicating over an input/output ("I/O") bus. Digital processing systems also often employ a cache memory to overcome the slow operating speed of secondary memory devices (typically referred to as main memory) coupled to the I/O bus. In the prior art, the secondary memory devices typically consist of dynamic random access memories ("DRAMs") while the cache memories consist of static random access memories ("SRAMs").
FIG. 1 shows a generalized example of a digital processing system using two cache memories. In particular, system 100 comprises a processor (110) coupled to a main memory (DRAM 125) via I/O bus 120. System 100 also includes two cache memories (cache 105 and cache 115) coupled to processor 110. Cache 115, which is sometimes referred to as a level 2 cache, may be used to store a small subset of the data resident in DRAM 125. Similarly, cache 105, which is sometimes referred to as a level 1 cache, may also be used to store a small subset of the data resident in DRAM 125. Typically, cache 105 is located on the same semiconductor substrate which includes processor 110.
In system 100, cache 105 and cache 115 allow processor 110 to bypass data transfers along I/O BUS 120 by providing a temporary storage medium. To further bypass data transfers along I/O BUS 120, processor 110 can update cache 105 and cache 115 without updating DRAM 125--typically, when data is written only into a cache the cache is referred to as a write back cache. The use of write back caches, however, requires that processor 110 includes additional logic and memory cells in the caches. The memory cells added to the caches identify whether a specific group of cache memory cells (referred to as a cache line) have been updated--the data stored in the additional memory cells is typically referred to as a "dirty bit."
FIG. 2 shows a typical example of a write back cache memory. In particular, cache 200 includes a tag array (230) and a data array (215) coupled to a decoder (210). Data array 215 includes a group of cache lines (216-216N) that store a copy of the data stored in main memory (for example DRAM 125 of FIG. 1). Similarly, tag array includes a group of tag lines (231-231N) that determine the main memory location associated with data stored in data array 215.
As illustrated in FIG. 2, cache 200 includes decoder 210. Decoder 210 includes an address (205) input and a clock (CLK 206) input. A processor (for example processor 110 of FIG. 1) coupled to cache 200 uses decoder 210 to store or retrieve data from cache 200. In particular, to access a cache line the processor generates a decoded address corresponding to a specific main memory address on address 205. In response to the decoded address, decoder 210 determines whether the main memory address resides within cache 200. Provided, the main memory address resides within cache 200, decoder 210 accesses a cache line in data array 215 and a tag line of tag array 230 via a word line.
FIG. 2 shows a word line (WL 225) used to access cache line 216 in data array 215 and tag line 231 in tag array 230. FIG. 2 also shows a dual port memory cell 240 included in tag line 231. Dual port memory cell 240 is coupled to decoder 210 via WL 225 and WL 226. Typically, dual port memory cell 240 stores a dirty bit indicating whether the information resident in the selected cache line is the updated version of the information resident in the main memory. Accordingly, the dirty bit allows a processor to determine which memory (main memory, a level one cache, or a level two cache) includes the most current data, thus reducing the chances of data corruption. For example, if a processor writes data to cache line 216, the processor sets the dirty bit value in dual port memory cell 240 to a first value until the data is transferred to main memory. Thus, the processor is able to determine which memory element includes the most current value by examining the values stored in dual port memory cells. Typically, dual port memory cells have three functional modes--a read/modify write mode, a read only mode, and a write only mode. During the read/modify write mode, the dirty bit of the dual port memory cell is read and re-written in one clock cycle.
One disadvantage of prior art cache systems results during a write only mode. Specifically, the data lines coupled to the dual port memory cell do not have a dedicated read and write capability.
Another disadvantage of prior art cache systems results in the operation of word lines coupled to the dual port memory. Specifically, the word lines coupled to the dual port memory have a clock phase relation that increases the logic size of the decoder coupled to the dual port memory cell.